The present invention relates to an IC tester for testing an IC by supplying test pattern signals to the IC and comparing response outputs from the IC and expected-value signals, and more particularly to an IC tester capable of correcting relative phase differences between a plurality of test pattern signals or a plurality of strobe signals for logic determination of the response output from the IC being tested.
IC testers of the type described supply a plurality of test pattern signals simultaneously to a plurality of terminal pins of an IC being tested. One IC test determines whether the IC being tested will operate properly or not when relative phases of the test pattern signals are varied. Furthermore, parallel response outputs from the terminal pins of the IC are subjected to logic decision with relative phases shifted to determine whether the IC produces a proper output. When the relative phases of the test pattern signals are excessively shifted due to a temperature change or with time, no proper test can be expected. When relative phases of the strobe signals are shifted, no correct test results can be obtained. Such shifting of the relative phases is caused by differences between travel times for signals transmitted after the test pattern signals have been prepared until they are supplied to the IC being tested. Therefore, variable delay circuits are inserted in the signal paths, and their delay settings are adjusted to equalize the travel times for the signal paths. However, the travel times tend to differ from each other due to a change in ambient temperature and with time. Since the changing portion in the waveform of each test pattern signal is inclined and logic circuits process signals by determining them as being of a high or low logic level above or below a certain threshold value, a change in the output level of pattern signals (a synchronous signal) in one test causes a shifting of relative phases with respect to pattern signals in another test. The positions of terminal pins such as for address and data pins of an IC memory vary from IC to IC, so that pin positions to which test pattern output signals are supplied need to be switched around, a procedure which causes relative phases to be shifted. It is time-consuming and tedious to adjust the variable delay circuits each time an IC of a different type is to be tested.
It has been the customary practice to adjust the variable delay circuits for calibration to eliminate shifting of relative phases between the test pattern signals and between the strobe signals from a desired phase relationship. Calibration to enable an IC tester to perform desired functions has been described by the present inventor in "A 100 MHz Test Station for High Speed LSI Testing", Digest of Papers, 1979 Test Conference, Cherry Hill, N.J., Oct. 23-25, CH 1509-9/79/0000-0369. This paper however does not show how calibration should be carried out.